Space Radiation Effects on Electronics – Single Event Effects

In the last post, Space Radiation Effects on Electronics – DDD Effects, we described the Displacement Damage Dose (DDD) effects. With that, we have concluded the cumulative effects. In this post, we will explain what Single Event Effects (SEE) are and what their impact on space electronics is.

Radiation Effects

Emerging commercial space technologies and budget limitations have created the need for a reduced cost of a spacecraft or space program. There seems to be a rise in demand for optimising system requirements (power, volume, weight), while also maintaining mission reliability. However, these emerging space technologies are often vulnerable to Single Event Effects or SEEs.

In space, cosmic rays and high energy protons are the two significant causes of SEEs. These heavy ions (Z>=2) and protons are abundant in space, thus they can cause SEEs in electronic devices and technologies. Digital devices such as FPGAs, microprocessors, and memory devices are most susceptible to SEEs.

In order to ensure the reliability of semiconductor devices and pave the way for successful systems in the harsh environment of space, all mission-critical systems must be tested for both TID and SEE. However, testing the SEE performance of a device is more complicated than checking the TID performance. This is mainly due to the increasing complexity of modern digital devices, the different manifestations of these effects and the fact that testing for single event effects takes place during radiation exposure while TID testing does not.

Single Event Effects

Single Event Effects (SEE) are electronic events caused by one highly energetic particle. They can create soft errors such as Single Event Upset (SEU), Single Event Transient (SET) and hard errors such as Single Event Latch-up (SEL), Single Event Gate Rupture (SEGR) and Single Event Burnout (SEB). The severity of SEEs depends on the type of the effect and how critical the system is.

Experiments have shown that there is a critical threshold energy deposited from an incident ion or proton is needed to trigger a SEE.

For protons, this energy deposition usually takes place through nuclear interactions which result in recoil ions that ionise the impact location’s neighbourhood. Most devices experience SEEs for incident protons of energy 10 MeV and above while recent research points to a 1.5-3 MeV acute sensitivity for modern electronics.

Regarding heavy ions, SEE is triggered via direct ionisation along its path inside the device. In that case, the more convenient energy loss metric is not particle Energy but Linear Energy Transfer (LET) which is the rate of energy loss per unit length on a material. The most common unit used for it is MeV-cm2/mg.

Commercial devices are susceptible to ions of LET as low as a couple of MeV-cm2/mg. More resistant devices present a threshold LET between 15 and 60 MeV-cm2/mg. Last, devices with a LET threshold higher than 150 MeV-cm2/mg are considered SEE-immune and reliable even at the harshest interplanetary environments.

As with the other radiation effects that we discussed, the expected on-orbit rate of SEUs depends on the radiation environment, that is energy flux spectrum of charged particles, and the specific device.

SEUs records during LEO missions such as PROBA-II and SAC-D observe an average error rate ranging from 0.1 to 1 SEU/day for commercial devices. These single event upset rates can decrease by a minimum of five orders of magnitude for radiation hardened counterparts.

As mentioned before in this article, SEEs can be regrouped into two categories: soft errors (non-destructive) and hard errors (destructive):

SOFT ERRORS (Non-Destructive):

  • SEU – Single Event Upset
    SEU is a change of state of an electronic device storage element caused by a single ionizing particle. These events usually do not affect the reliability and function of a system over time and are easier to fix than hard errors. SEEs that result in one upset are called Single Bit Upsets (SBU), whilst those resulting in multiple upsets are named Multiple Cell Upsets (MCU). Several upset cells that are part of the same logic word are referred to as Multiple Bit Upsets (MBU). MBU causes multiple bit errors during one measurement. The SEUs usually affect latches, memory devices, and sequential logic.
  • SET – Single Event Transient
    SET occurs when the motion of charges by a single particle, causes a temporary (transient) voltage glitch. This transient can recover quickly without other actions needed to clear the error condition. Nevertheless, the danger of it being latched at a wrong logic level is present and higher in faster devices. SETs affect mostly analog and mixed-signal circuits.

  • SEFI – Single Event Functional Interrupt
    SEFI occurs when a disturbance of state registers interrupts the normal operation of circuits and the affected device enters a different operation mode or locks-up. In essence, SEFIs are SEUs taking place at the control sections of the circuit. These are more difficult to restore than other SEUs and usually, a software reset or a power-cycling is required.

HARD ERRORS (Destructive):

  • SEL – Single Event Latch-up
    SEL is a type of hard fault which is usually catastrophic to the system. The passage of a single energetic particle can trigger a parasitic PNPN structure drawing an abnormally high operating current. If the power input is not reset in time the device is at risk of suffering from a potentially disastrous overcurrent episode that can result in structure overheating and melting. The SEL can occur with Complementary Metal-Oxide-Silicon CMOS and BiCMOS devices in structures such as the electrostatic discharge (ESD) or overvoltage protection circuits. SELs do not take place in Silicon-on-Insulator (SOI) devices, which suppress any parasitic PNPN structures (thyristor).

  • SESB – Single Event Snapback
    SESB is another self-sustained high-current state caused by radiation. Its effect resembles an SEL but the mechanism differs entirely. A snapback takes place within a single NMOS structure when the electric field between Source and Drain is high. During a radiation event, the ionisation charge can trigger avalanche multiplication conditions and activate a parasitic NPN bipolar transistor between Drain and Source. The amount of current drawn is much smaller compared to a latch-up but it can still result in local overheating of that structure. SESB has been observed in NMOs structures and SOI devices and can be removed with lowering the drain bias below the avalanche multiplication region.

  • SEHE – Single-Event Hard Errors
    Single-Event Hard Errors, also referred to as “stuck” bits, are memory bits that are unable to be changed by a write-process, therefore rendered non-functional. The mechanism behind this is attributed to microdose effects induced by single ions. As with general TID accumulation, heavy ions themselves too create hole traps in the SiO2/Si interfaces. However, the density of these traps is highly peaked around the ion track in contrast to the roughly isotropic profiles induced by protons, electrons or gamma radiation. This streak of traps is able to establish leakage paths and “pin” the affected transistor to either a closed or open state. As a result, the memory cell gets “pinned” to either a “1” or “0” state.

Conceptual drawing of SEEs in a CMOS digital IC. A hybrid substrate structure (bulk+SOI) is assumed for illustrative purposes.
  • SEDR – Single-Event Dielectric Rupture
    SEDR is caused by an ionized particle inside the high-field region of a dielectric which creates a conductive path, resulting in a current-jump phenomenon (jump in the core power supply). However, SEDR is rather considered an academic interest, as it is mostly observed in testing and not in space.

  • SEGR – Single Event Gate Rupture
    SEGR is caused by the passage of a heavy ion through the neck area of a Double Diffused Metal Oxide Semiconductor (DMOS) power transistor when in the OFF state; The generated holes drift towards the gate and accumulate at the silicon-gate oxide interface. If not diffused or recombined at the lateral p-regions in time, they develop a local electric field exceeding the intrinsic breakdown dielectric potential. This results in the dielectric breaking down and short-circuiting the gate with the substrate. The SEGR affects mainly the power MOSFET and recently has been observed in MOS-based digital and linear ICs resulting in destructive consequences. It is also often observed simultaneously with Single Event Burnout (SEB) in power MOSFETs.

  • SEB – Single Event Burnout
    SEB is caused by a single energetic particle charge (primarily heavy ions) that results in localized high-current state in the body of the device. This type of hard error often results in catastrophic failure. The SEB affects primarily bipolar transistors and N-channel power MOSFET in space, but has also been observed in high voltage diodes in terrestrial applications.
Understanding these unique system failures and the ability to develop robust mitigation strategies is critical for space missions.

Stay tuned for more information about the existing mitigation methods and to learn more about the unique offering of Space Talos.

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